Because each EDA tool is its own server, you load Verilator for simulation without dragging in KLayout's layout tools, which keeps the exposed surface matched to the task. The natural-language layer means you can ask for a synthesis or a DRC run in plain terms, but every server still depends on the underlying tool being installed.
Eight MCP servers for electronic design automation, each wrapping a standard EDA tool and exposing its operations, with a natural-language interface on top.
- Yosys — yosys_synth, yosys_analyze and yosys_show for synthesis, analysis and circuit diagrams
- Verilator — verilator_compile, verilator_simulate and verilator_testbenchgenerator for RTL simulation with auto-generated testbenches
- Verible — verible_lint, verible_format and verible_syntax for SystemVerilog linting, formatting and AST analysis
- GTKWave — gtkwave_open, gtkwave_convert and gtkwave_analyze_timing for waveform viewing and timing measurement
- KLayout — klayout_run_drc, klayout_convert_layout and klayout_extract_layers for IC layout and design-rule checking
- AnySilicon — calculate_die_per_wafer for die-per-wafer yield across 150mm to 450mm wafers
- OpenLane — openlane_run_flow plus per-stage tools for synthesis, floorplanning, placement, CTS and routing
- A semiconductor supply-chain server — find_ip_vendors, find_asic_services and compare_vendors
Each server lives in its own directory and wraps a real EDA tool that has to be installed — Yosys, Verilator, Verible, GTKWave, KLayout, OpenLane — so you set up only the ones you use. The servers are Node and Python; register the one you need with your MCP client. OpenLane runs its flow in a Docker or Podman container.